Siemens and TSMC expand AI tools for chip design

Siemens and Taiwan Semiconductor Manufacturing Co. are expanding their work on software and processes intended to make semiconductor development faster and more automated. In an announcement published by news.siemens.com, Siemens said the companies will extend design-enablement activities across digital, custom and advanced 3D integrated-circuit workflows.

A central element is an artificial-intelligence agent that can identify and help correct design rule check (DRC) violations. The system combines Siemens’ Calibre software with Aprisa and Solido technologies, bringing automated analysis and repair into both digital and custom chip-design flows. The stated aim is to reduce repetitive engineering work, improve workflow efficiency and help companies reach tapeout sooner.

AI moves into chip verification

DRC is a critical stage in semiconductor development. It tests whether a design complies with the manufacturing rules associated with a particular process. As chip designs become more complicated, engineers must deal with more violations and more interactions between design tools, making manual investigation time-consuming.

The new workflow builds on Calibre Check Assist, which supplies contextual information and design-rule guidance during DRC debugging. Aprisa AI and Solido Fuse add capabilities intended to identify, interpret and address violations across different design environments. Siemens also described agentic functions for custom IC development, in which software can carry out linked tasks rather than simply responding to a single instruction.

The broader collaboration includes the Fuse EDA AI System and Fuse EDA AI Agent. Siemens said these tools are designed for autonomous, extended and self-checking electronic design automation workflows. They can reason through multi-stage assignments, coordinate activity across several EDA products and repeatedly assess results. NVIDIA AI technologies are being used with Fuse EDA AI Agent to improve token efficiency and performance on long-running engineering workloads.

Aprisa is also being used for AI-supported place-and-route and digital implementation. These capabilities are intended to automate labour-intensive steps, apply design-specific guidance and help teams reach design convergence. Together, the companies say the work covers activities from initial design through tapeout.

Scaling 3D chip and package design

The partnership extends beyond conventional chip design to TSMC’s 3DFabric technologies, which support advanced three-dimensional integration and packaging. Siemens has enabled multi-machine operation in Calibre 3DStack Advanced for inter-chiplet antenna verification, including support for TSMC-SoIC, a wafer-level chip-stacking platform.

Certification work is also under way for chip-on-wafer-on-substrate designs using local silicon interconnect, known as CoWoS-L. Siemens said these developments provide the scalability and runtime performance required by increasingly complex 3D designs. The companies have also reported performance improvements in the Interface Check Flow for TSMC-SoW.

Other joint activities involve chip-package co-design and broader 3Dblox support. Siemens and TSMC are working with major mutual customers on these flows, while Aprisa is being developed for pre-simulation-driven die-to-die auto-routing. The function is intended to derive routing configurations that meet signal-integrity requirements.

Siemens’ portfolio is also being applied to thermal, electrical and optical work. Solido Simulation Suite, Calibre xACT and Calibre 3DThermal support initiatives involving 3D ICs, multiphysics design and silicon photonics. Calibre 3DThermal has certification for static and transient thermal analysis of TSMC 3DFabric technologies and the TSMC A16 process. It has also been enabled for a system-on-wafer thermal reference flow, while work continues on the thermal reference flow for TSMC-COUPE, or Compact Universal Photonic Engine.

Process certification and training

The companies are continuing to certify Siemens tools for TSMC’s newer process technologies. Calibre nmDRC, Calibre nmLVS, Calibre xACT and Calibre PERC have been certified for TSMC’s A14 process.

Solido Simulation Suite has been certified for SPICE accuracy on TSMC N3C, A16 and A14 technologies. Siemens said this supports verification work for analog, radio-frequency and memory designs. Its tools also contribute to custom-design reference flows covering reliability concerns such as chip aging, self-heating and safe operating areas, alongside variation-aware verification and automated cell optimization.

The mPower tool is certified for transistor-level IR-drop and electromigration analysis on TSMC N2P digital and analog designs and N3C analog designs. Further work is continuing on N2 and N3 custom-design reference flows, while certification for Aprisa and mPower analog software on A14 remains in progress.

The relationship also includes education. Siemens Xcelerator Academy, which offers self-paced online material for its EDA products, is now available to TSMC Design Center Alliance partners as well as shared customers. A recently released tutorial covers an end-to-end digital implementation flow based on TSMC’s 5nm process technology, broadening access to the design methods supported by the collaboration.